In the rapidly advancing world of semiconductor technology, the relentless pursuit of smaller, faster, and more energy-efficient computer chips is critical to powering the next wave of innovation—from artificial intelligence mega-data centers to cutting-edge medical devices and ubiquitous consumer electronics. At the frontier of this evolution lies extreme ultraviolet (EUV) lithography, a sophisticated method capable of etching circuit patterns at the nanometer scale. However, the intrinsic complexities and astronomical costs associated with current EUV lithographic systems have presented formidable barriers to wider adoption and scalability. Now, a groundbreaking proposal from Professor Tsumoru Shintake of the Okinawa Institute of Science and Technology (OIST) offers a transformative vision for this technology, promising to revolutionize semiconductor manufacturing with unprecedented precision, reduced complexity, and drastically lower costs.

EUV lithography operates by harnessing light with an extraordinarily short wavelength—just 13.5 nanometers—which enables the creation of incredibly fine features on silicon wafers. The process begins when this EUV light is generated and meticulously channeled through an illumination system towards a reflective photomask imprinted with the target circuit design. Upon reflection, this patterned light passes through a projector system composed of precisely curved mirrors, which shrink and focus the intricate design onto a silicon wafer. Subsequent processing etches the illuminated pattern into the wafer’s surface, forming the foundational architecture of semiconductor chips. Crucial to pushing the envelope of miniaturization is the numerical aperture (NA) of these systems—a parameter that defines the range of angles over which the system can accept or emit light. Higher NA values correlate directly to finer resolution capabilities, enabling denser packing of transistors and circuit elements.

Despite the theoretical promise of high-NA EUV lithography, practical implementation has been fraught with challenges. The early explorations into high-NA configurations favored simple in-line setups wherein the photomask, projector, and wafer are aligned along a single optical axis. This streamlined arrangement, while intuitively appealing, introduced significant optical aberrations such as distortions and blurring that intensified with increasing NA. These so-called “mask 3D effects” arise due to the complex interplay of light reflections on the three-dimensional topography of the photomask, adversely affecting pattern fidelity and ultimately the electrical performance of the fabricated chips.

Confronting these longstanding obstacles, Professor Shintake embarked on an ambitious reimagining of the illumination and projection components integral to high-NA EUV lithography. His initial foray involved evaluating the feasibility of a minimalist projector design consisting of a single pair of mirrors—one concave and one convex—with the potential to deliver high-resolution imagery while suppressing aberrations. Although this simplistic approach did not yield immediate success, continued exploration led to a sophisticated two-stage projection configuration. Each stage utilizes a concave-convex mirror pair arranged to optimize optical performance. Remarkably, simulations revealed that carefully orchestrated multiple reflections between these mirrors could cancel out deleterious optical defects, preserving the high numerical aperture without compromising image quality.

These insights emerged from extensive computational modeling conducted using OpTaliX, an advanced optical simulation software. Through meticulous parameter optimization, including mirror curvature adjustments and precise spatial positioning, Shintake and his collaborators delineated an optical path that maintains high resolution while mitigating the distortive mask 3D effects. The theoretical framework underscores the power of optical engineering in overcoming fundamental diffraction and interference phenomena—challenges that have hampered high-NA EUV lithography efforts for decades.

Beyond the technical elegance of the design, the proposed system carries profound economic implications. Current state-of-the-art EUV lithography machines reportedly cost hundreds of millions of euros each, placing them out of reach for all but the largest semiconductor manufacturers. In stark contrast, Shintake’s approach promises to slash these costs dramatically—potentially to just a quarter of today’s expenditures—thus democratizing access to cutting-edge lithography and accelerating development cycles across the industry.

The ramifications extend well beyond chip manufacturing economics. The International Energy Agency forecasts that by 2030, global data center electricity consumption will double, driven largely by the proliferation of energy-intensive artificial intelligence applications. Higher-density chips fabricated with the new high-NA technology would feature electronic pathways shortened by virtue of their finer architectural detail, reducing signal travel distance and thereby minimizing energy loss during computation. Moreover, lower heat emission from these denser chips implies diminished cooling requirements, collectively resulting in meaningful reductions in power consumption and operational costs for data centers worldwide.

As part of his next research phase, Professor Shintake and his team aim to transition from simulation to realization by constructing a physical prototype of the novel high-NA EUV lithography system. This endeavor will necessitate overcoming engineering challenges such as fabricating mirrors with near-perfect reflectivity and minimal surface defects—criteria assumed in simulations but challenging to achieve in practice. Nonetheless, the initial groundwork laid by this study establishes a compelling blueprint for transforming semiconductor fabrication.

In addition to enabling finer patterning capabilities, the simplified in-line projector design enhances overall system robustness and manufacturability. By aligning the photomask, projector, and wafer along a single axis with optimized mirror pairs, the architecture reduces alignment complexities and optical component counts, thereby facilitating easier maintenance and potentially accelerating throughput rates on the manufacturing floor.

Innovations like Shintake’s not only refresh the physics of lithographic imaging but may also catalyze novel computing paradigms by significantly pushing the achievable limits of miniaturization. As industry demand for memory density and logic efficiency mounts exponentially, high-NA EUV lithography could unlock pathways to next-generation chip designs exhibiting superior speed, reduced energy consumption, and lower production costs, collectively powering advancements in artificial intelligence, quantum computing, and ubiquitous digital technologies.

Ultimately, this research signals a pivotal juncture for semiconductor manufacturing, harnessing the power of optical science to surmount entrenched technical and financial hurdles. By reducing the cost and complexity of high-NA EUV lithography, Professor Shintake’s innovation promises transformative impacts on the silicon industry and beyond—enabling faster, greener, and more affordable electronics that will underpin the data-centric future of society.

Subject of Research: High numerical aperture (high-NA) extreme ultraviolet (EUV) lithography systems for semiconductor chip manufacturing

Article Title: High-NA in-line projector for EUV lithography

News Publication Date: June 12, 2026

Web References: http://dx.doi.org/10.1117/1.JMM.25.2.023801

Image Credits: Andrew Scott, Okinawa Institute of Science and Technology (OIST)

Tags: advanced photolithography techniquesEUV lithography cost reductionextreme ultraviolet lithography technologyhigh-NA lithography optical systemshigh-resolution semiconductor etchingnanometer scale circuit patterningOkinawa Institute of Science and Technology researchprecision optical systems for semiconductorsreflective photomask in lithographyscalable EUV lithography solutionssemiconductor chip manufacturing innovationTsumoru Shintake lithography proposal